{"id":1430,"date":"2024-08-14T13:58:02","date_gmt":"2024-08-14T05:58:02","guid":{"rendered":"https:\/\/swordofmorning.com\/?p=1430"},"modified":"2025-10-09T13:54:44","modified_gmt":"2025-10-09T05:54:44","slug":"rv1126-07","status":"publish","type":"post","link":"https:\/\/swordofmorning.com\/index.php\/2024\/08\/14\/rv1126-07\/","title":{"rendered":"RV1126 \u4fee\u6539VOP\u7684PLL"},"content":{"rendered":"

<\/div><\/p>\n

\u4e00\u3001\u53c2\u8003\u8d44\u6599<\/h2>\n
    \n
  1. PLL\u786c\u4ef6\u8bbe\u8ba1\uff1a\u300aRockchip RV1109&RV1126TRM V1.0 Part1\u300b\u4e2d\u7684\u3010Fig. 5-3 PLL Block Diagram\u3011\u3002<\/li>\n
  2. PLL\u76f8\u5173\u63cf\u8ff0\uff1a\u300aRockchip Clock \u5f00\u53d1\u6307\u5357\u300b\u4e2d\u7684\u30102.2.1 PLL\u3011\uff0c\u6ce8\u610f\uff0c\u8be5\u6587\u6863\u7684\u8868\u793a\u548cRV1126\u7565\u6709\u5dee\u5f02\uff0c\u4ec5\u4f5c\u57fa\u672c\u53c2\u8003\u3002<\/li>\n
  3. Linux\u4e2d\u7684\u65f6\u949f\u914d\u7f6e\uff1a\u300aRockchip \u65f6\u949f\u914d\u7f6e\u8be6\u7ec6\u8bf4\u660e\u300b\uff0c\u6ce8\u610f\uff0c\u76ee\u524d\u7684SDK\u4e0b\uff0c\u8be5\u6587\u6863\u7248\u672c\u4e3a1.0\uff0c\u662fRK3399\u53c2\u8003\u6587\u6863\uff0c\u4ec5\u4f5c\u57fa\u672c\u53c2\u8003\u3002<\/li>\n<\/ol>\n

    \u4e8c\u3001\u95ee\u9898\u8d77\u56e0<\/h2>\n

      \u9694\u58c1\u8001\u54e5\u60f3\u8981\u5c06RV1126\u7684dclk_vop<\/code>\u4fee\u6539\u4e3a65MHz<\/code>\uff0c\u4ee5\u9002\u914d1024x768@60Hz<\/code>\u7684\u5206\u8fa8\u7387\u3002\u4f46\u5728\u4f7f\u7528\u547d\u4ee4echo 65000000 > \/sys\/kernel\/debug\/clk\/dclk_vop\/clk_rate<\/code>\u8bbe\u7f6e\u7684\u65f6\u5019\uff0c\u5f97\u5230\u7684\u9891\u7387\u662f\uff1a62526316<\/code>\u3002\u4f46\u662f\u5982\u679c\u8bbe\u7f6e54MHz(1024x768@50)<\/code>\u6216\u800574.25MHz(1920x1080@60)<\/code>\u90fd\u53ef\u4ee5\u6b63\u5e38\u914d\u7f6e\u3002<\/p>\n

      \u56e0\u6b64\u6211\u4eec\u6709\u5982\u4e0b\u5047\u8bbe\uff1a<\/p>\n

      \n
    1. \u9a71\u52a8\u662f\u6b63\u5e38\u7684\uff0c\u5305\u62ecclk_change_rate()<\/code>\u548cclk_round_rate()<\/code>\uff1b<\/li>\n
    2. \u82af\u7247\u4e2d\u4ecePLL\u5230dclk_vop\u7684\u65f6\u949f\u9891\u7387\u65e0\u6cd5\u5206\u914d65MHz<\/code>\u3002<\/li>\n<\/ol>\n

      \u4e09\u3001\u9a8c\u8bc1\u95ee\u9898<\/h2>\n

        \u6211\u4eec\u4f7f\u7528cat \/sys\/kernel\/debug\/clk\/clk_summary<\/code>\u6765\u67e5\u770b\u5f53\u524d\u7684\u65f6\u949f\u6811(\u8fd9\u91cc\u53ea\u663e\u793a\u4e86\u4e00\u90e8\u5206)\uff1a<\/p>\n

                                       enable  prepare  protect                                duty\n   clock                          count    count    count        rate   accuracy phase  cycle\n---------------------------------------------------------------------------------------------\n    pll_hpll                          1        1        0  1400000000          0     0  50000\n       hpll                           1        2        0  1400000000          0     0  50000\n          clk_npu_np5                 0        0        0   186666667          0     0  50000\n          clk_npu_div                 0        1        0   700000000          0     0  50000\n             clk_core_npu             0        2        0   700000000          0     0  50000\n                clk_core_npupvtm       0        0        0   700000000          0     0  50000\n    pll_gpll                          1        1        0  1188000000          0     0  50000\n       gpll                          14       36        0  1188000000          0     0  50000\n          dclk_vop_div                1        1        0    62526316          0     0  50000\n             dclk_vop_mux             1        1        0    62526316          0     0  50000\n                dclk_vop              1        3        0    62526316          0     0  50000\n             dclk_vop_fracdiv         0        0        0    62526316          0     0  50000<\/code><\/pre>\n
      \u6211\u4eec\u53ef\u4ee5\u770b\u5230\uff0cdclk_vop<\/code>\u4f7f\u7528\u7684\u65f6\u949f\u6e90\u6765\u81eagpll<\/code>\uff0c\u5176\u65f6\u949f\u662f1188000000<\/code>\u3002\u5982\u679c\u6309\u716754MHz<\/code>\u5206\u9891\uff0c\u5176\u5206\u9891\u500d\u6570\u4e3a22\uff1b\u5982\u679c\u6309\u716774.25MHz<\/code>\u5206\u914d\uff0c\u5176\u5206\u9891\u500d\u6570\u4e3a16\uff1b\u5982\u679c\u6309\u716765MHz<\/code>\u5206\u9891\uff0c\u5176\u5206\u9891\u500d\u6570\u4e3a18.27\uff0c\u56e0\u4e3aPLL out\u540e\u7684\u5206\u9891\u5668\u53ea\u80fd\u6309\u7167\u6574\u6570\u500d\u5206\u9891\uff0c\u56e0\u6b64\u5c06\u5176\u8c03\u6574\u4e3a19\uff0c\u5f97\u523062526315<\/code>\uff0c\u548ccat<\/code>\u51fa\u6765\u7684\u6570\u636e\u5dee1Hz<\/code>\uff0c\u5c5e\u4e8e\u8bef\u5dee\u8303\u56f4\u3002<\/p>\n
      \u56db\u3001\u89e3\u51b3\u95ee\u9898<\/h2>\n
      4.1 \u4fee\u6539vop\u7684\u65f6\u949f\u6e90<\/h3>\n
        \u6211\u4eec\u7ffb\u9605dtsi<\/code>\u548c\u6587\u68632\u53ef\u4ee5\u53d1\u73b0\uff0cRV1126\u6709\u4ee5\u4e0b\u51e0\u4e2aPLL\uff1a<\/p>\n
        \n
      1. APLL\uff0cCPU\u7684\u65f6\u949f\uff1a\u4e00\u822c\u53ea\u7ed9CPU\u4f7f\u7528\uff0c\u56e0\u4e3aCPU\u4f1a\u53d8\u9891\uff0cAPLL\u4f1a\u6839\u636eCPU\u8981\u6c42\u7684\u9891\u7387\u53d8\u5316\u3002<\/li>\n
      2. DPLL\uff0cDDR\u7684\u65f6\u949f\uff1a\u4e00\u822c\u53ea\u7ed9DDR\u4f7f\u7528\uff0c\u56e0\u4e3aDDR\u4f1a\u53d8\u9891\uff0cDPLL\u4f1a\u6839\u636eDDR\u8981\u6c42\u7684\u9891\u7387\u53d8\u5316\u3002<\/li>\n
      3. GPLL\uff0c\u63d0\u4f9b\u603b\u7ebf\u3001\u5916\u8bbe\u65f6\u949f\u505a\u5907\u4efd\uff1a\u4e00\u822c\u8bbe\u7f6e\u5728594M\u6216\u80051200M\uff0c\u4fdd\u8bc1\u57fa\u672c\u7684100\u3001200\u3001300\u3001400M\u7684\u65f6\u949f\u90fd\u6709\u8f93\u51fa\u3002<\/li>\n
      4. CPLL\uff0cGMAC\u6216\u8005\u5176\u4ed6\u8bbe\u5907\u505a\u5907\u4efd\uff1a\u4e00\u822c\u53ef\u80fd\u662f400\u3001500\u3001800\u30011000M\uff0c\u6216\u8005\u662f\u7ed9Lcdc\u72ec\u5360\u4f7f\u7528\u3002<\/li>\n
      5. NPLL(HPLL)\uff0c\u7ed9\u5176\u4ed6\u8bbe\u5907\u505a\u5907\u4efd\uff1a\u4e00\u822c\u53ef\u80fd\u662f1188M\uff0c\u6216\u8005\u7ed9Lcdc\u72ec\u5360\u4f7f\u7528\u3002<\/li>\n<\/ol>\n
        \u56e0\u6b64\uff0c\u6211\u4eec\u4ece\u65f6\u949f\u6811\u4e2d\u53d1\u73b0hpll<\/code>\u7684\u8bbe\u5907\u6700\u5c11\uff0c\u6211\u4eec\u5c06dclk_vop_div<\/code>\u8fc1\u79fb\u81f3hpll<\/code>\u4e4b\u540e\u500d\u9891\u66f4\u5bb9\u6613\u66f4\u6539\u3002<\/p>\n
          \u8fdb\u4e00\u6b65\u7684\uff0c\u5982\u679c\u6211\u4eec\u4e0d\u60f3\u8981\u4fee\u6539dclk_vop_div<\/code>\u7684\u65f6\u949f\u6e90\uff0c\u90a3\u4e48\u5c31\u9700\u8981\u4fdd\u8bc1\u5f53\u524d\u65f6\u949f\u6e90gpll<\/code>\u53ef\u4ee5\u5206\u9891\u51fa65MHz<\/code>\u3001\u540c\u65f6\u517c\u5bb91188000000<\/code>\u3002\u6211\u4eec\u8ba1\u7b97\u53d1\u73b0\uff0c\u6211\u4eec\u9700\u8981PLL<\/code>\u51fa77.22GHz<\/code>\u624d\u80fd\u6ee1\u8db3\u8981\u6c42\u3002\u6211\u4eec\u901a\u8fc7\u6587\u68631\u4e2d\u7684PLL\u67b6\u6784\u53ef\u4ee5\u8ba1\u7b97\u51fa\uff0c\u5176\u6700\u5927\u9891\u7387\u652f\u6301\u523038.4GHz<\/code>\uff0c\u56e0\u6b64\u65e0\u6cd5\u5b9e\u73b0\u517c\u5bb9\u3002\u4e8e\u662f\u6211\u4eec\u9009\u62e9\u5c06dclk_vop_div<\/code>\u7684\u65f6\u949f\u6e90\u66ff\u6362\u4e3ahpll<\/code>\uff0c\u8ba1\u7b97\u53d1\u73b0\uff0c\u53ea\u9700\u8981\u5c06\u5176\u65f6\u949f\u63d0\u5347\u523018.2GHz<\/code>\u5373\u53ef\u6ee1\u8db3\u517c\u5bb965MHz<\/code>\u548c700MHz<\/code>\u7684\u9700\u6c42\u3002\u4f46\u5728\u8bbe\u5907\u6811\u4e2d\uff0c\u5176\u4f7f\u752832bits\u7684\u6570\u636e\u6765\u5b58\u653e\u65f6\u949f\uff0c\u56e0\u6b64\u6700\u9ad8\u4e0a\u9650\u53ea\u67094GHz<\/code>\u591a\u4e00\u4e9b\uff0c\u56e0\u6b64\u6211\u5c06\u5176\u4fee\u6539\u4e3a1.82GHz<\/code>\uff0c\u4ee5\u907f\u514dPLL\u4e4b\u540e\u540e\u5206\u9891\u5668\u4e0d\u591f\u505a\u5230\u66f4\u9ad8\u6bd4\u4f8b\u7684\u5206\u9891\u3002<\/p>\n
          \u6211\u4eec\u5728rv1126.dtsi<\/code>\u4e2d\u505a\u5982\u4e0b\u4fee\u6539\uff1a<\/p>\n
        cru: clock-controller@ff490000 {\n    compatible = "rockchip,rv1126-cru";\n    reg = <0xff490000 0x1000>;\n    rockchip,grf = <&grf>;\n    #clock-cells = <1>;\n    #reset-cells = <1>;\n\n    assigned-clocks =\n        <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,\n        <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,\n        <&cru PLL_HPLL>, <&cru ARMCLK>,\n        <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,\n        <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,\n        <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,\n        <&cru HCLK_PDCORE_NIU>;\n    assigned-clock-rates =\n        <32768>, <1188000000>,\n        <100000000>, <500000000>,\n        \/\/ <1400000000>, <600000000>,\n        <1820000000>, <600000000>,\n        <500000000>, <200000000>,\n        <100000000>, <300000000>,\n        <200000000>, <150000000>,\n        <200000000>;\n    assigned-clock-parents =\n        <&pmucru CLK_OSC0_DIV32K>;\n};<\/code><\/pre>\n
        4.2 \u4fee\u6539dclk_vop_div\u7684\u65f6\u949f\u6e90<\/h3>\n
          \u7ecf\u8fc7\u6211\u4eec\u57284.1\u4e2d\u7684\u5206\u6790\uff0c\u73b0\u5728\u6211\u4eec\u9700\u8981\u5c06dclk_vop_div<\/code>\u7684PLL\u4fee\u6539\u4e3ahpll<\/code>\u3002\u6211\u4eec\u4fee\u6539\u7684\u6587\u4ef6\u662fkernel\/driver\/clk\/rockchip\/clk-rv1126.c<\/code>\uff0c\u9996\u5148\u6dfb\u52a0\u4ec5\u6709hpll<\/code>\u7684\u5b9a\u4e49\uff1a<\/p>\n
        #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE\nPNAME(mux_gpll_usb480m_cpll_xin24m_p)   = { "gpll", "usb480m", "cpll", "xin24m" };\nPNAME(mux_armclk_p)         = { "gpll", "cpll", "apll" };\nPNAME(mux_gpll_cpll_dpll_p)     = { "gpll", "cpll", "dummy_dpll" };\nPNAME(mux_gpll_cpll_p)          = { "gpll", "cpll" };\nPNAME(mux_gpll_cpll_usb480m_xin24m_p)   = { "gpll", "cpll", "usb480m", "xin24m" };\nPNAME(mux_cpll_gpll_p)          = { "cpll", "gpll" };\nPNAME(mux_gpll_cpll_xin24m_p)       = { "gpll", "cpll", "xin24m" };\nPNAME(mux_cpll_hpll_gpll_p)     = { "cpll", "hpll", "gpll" };\nPNAME(mux_cpll_gpll_hpll_p)     = { "cpll", "gpll", "hpll" };\nPNAME(mux_gpll_cpll_hpll_p)     = { "gpll", "cpll", "hpll" };\nPNAME(mux_gpll_cpll_apll_hpll_p)    = { "gpll", "cpll", "dummy_apll", "hpll" };\n\/\/ ADD BEGIN\nPNAME(mux_hpll_p)   = { "hpll" };\n\/\/ ADD END<\/code><\/pre>\n
        \u63a5\u7740\u6211\u4eec\u5c06dclk_vop_div<\/code>\u7ed1\u5b9a\u7684PLL\u8bbe\u7f6e\u4e3amux_hpll_p<\/code>\u5373\u53ef\u3002<\/p>\n
        \/\/ Original: Bind to mux_gpll_cpll_p\nCOMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,\n        RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,\n        RV1126_CLKGATE_CON(14), 11, GFLAGS),\n\/\/ Modify: Bind to mux_hpll_p\nCOMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_hpll_p, 0,\n        RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,\n        RV1126_CLKGATE_CON(14), 11, GFLAGS),<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"
        \u4e00\u3001\u53c2\u8003\u8d44\u6599 PLL\u786c\u4ef6\u8bbe\u8ba1\uff1a\u300aRockchip RV1109&RV1126TRM V1.0 Part1\u300b\u4e2d\u7684\u3010Fig.  …<\/p>","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[46],"tags":[303],"amp_enabled":true,"_links":{"self":[{"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/posts\/1430"}],"collection":[{"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/comments?post=1430"}],"version-history":[{"count":3,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/posts\/1430\/revisions"}],"predecessor-version":[{"id":1433,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/posts\/1430\/revisions\/1433"}],"wp:attachment":[{"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/media?parent=1430"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/categories?post=1430"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/swordofmorning.com\/index.php\/wp-json\/wp\/v2\/tags?post=1430"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}